Adders are generally of five types:
1) Ripple Carry Adder:
The Ripple carry adder(RCA) consists of a building block named Half
Adder(HA) which is cascaded to form a Full Adder(FA). These building
blocks HAs and FAs are also the building blocks of all types of
adders.The n full adders are cascaded to form n bit RCA.
The full adder has three input pins(input Ai,input Bi,carryin Ci) and
two output pins(Sum and Ci+1).Its equations are:
Sum=Ai^Bi^Ci
Ci+1=Ai.Bi+Bi.Ci+Ai.Ci
2)Carry Lookahead Adder:
The Carry Lookahead Adder(CLA) reduces the delay as that in RCA. Let
Gi=Ai.Bi, and Pi=Ai^Bi, then Ci+1=Gi+Pi.Ci.
The expressions for Sum and Ci+1 is then defined completely in terms of
input pins rather wait for input carry to appear.
3)Carry Select Adder:
The carry select adder uses duplicate modules for each combination of
input carry(i.e. 1 and 0).The multiplexers then select the appropriate
sum and carry output according to the carry output of the preceding
stages.
Suppose your flip-flop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint .
Time for which data should be stable after the positive edge of clock is called as hold time constraint.
if any of these constraints are violated then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.
there are two equation:
1. Tcq + Tcomb> Tskew + Thold
2. Tcq + Tcomb<Tskew +T - Tsetup
Tcq is time delay when data enters the flip-flop and data comes at output of flip flop.
Tcomb is the logic delay between two flip flop.
Tskew is the delay of clock to flip flop: suppose there are two flip flop ,if clock reaches first to source flip flop and then after some delay to destination flip flop ,it is positive skew and if vice versa then negative skew.
so if you take 2 eq you will see that setup time is the determining factor of clock's time period.
You can divide the frequency of a clock by just implementing T Flip flop.
Give clock as clock input and tie the T input to logic 1.
XOR each bits of A with B (for eg A[0] xor B[0] ) and
so on. the o/p of 8 xor gates are then given as i/p to
an 8-i/p nor gate. if o/p is 1 then A=B.
One way is shorting the two inputs of the NAND gate and passing the input.
truth table:
A B output
1 1 0
0 0 1
The second way is passing the input to only one input(say A) of the NAND gate.Since the other input(say B) is floating, it is always logic one.
truth table:
A B output
1 1 0
0 1 1
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Aater Suleman (1 Comment) 21st of May 2011
Great list. i like the fact that you have embedded answers. I would prefer to have an option to hide the answers. I recently compiled a list of my own afters years of being both sides of the table:
I do not have answers on my page so I will link this site for people to come get answers. Great help!