Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal?
Submitted by: AdministratorPut even number of not gates between clocks of reg A and
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
Submitted by: Administrator
Reg B. The not gates will introduce delay between clock of
reg A and reg B.
Submitted by: Administrator
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