**1. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?**

put one bubble in front of xor gate....

**2. Explain Transmission Gate-based D-Latch?**

The Transmission-Gate input is connected to the D_LATCH

data input (D), the control input to the Transmission-Gate

is connected to the D_LATCH enable input (EN) and the

Transmission-Gate output is the D_LATCH output (Q)

**3. Give truth table for a Half Adder, Give a gate level implementation of the same?**

x y c s

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

**4. What are different Adder circuits you studied?**

Half Adder (for addition of two bits)

Full Adder (for addition of three bits)

Carry propagate adder

Carry save adder

Carry look ahead adder

Put even number of not gates between clocks of reg A and

Reg B. The not gates will introduce delay between clock of

reg A and reg B.

**6. Design a divide-by-3 sequential circuit with 50% duty circle now?**

incoming clock by ODD value as assigned in genric

CLK_DIV_BY generic with

50% duty cycle

------------------------------------------------------------

-----------

library IEEE;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

entity FDIV is

generic(

CLK_DIV_BY : INTEGER :=15; --Give the

odd value with which you want to divide the clock i.e.

3,5,7,9

COUNTVALUE : INTEGER :=4 --Give the bit

count of division ratio value.Ex upto 3= 2 bits; 5 to 7 =

3; 9 to 15 = 4 and so on..

);

port(

CLK : in std_logic;

CLR : in std_logic;

DIV: out std_logic

);

end FDIV;

--------------------------------------------------

Architecture beh of FDIV is

signal DIV_pos, DIV_neg :std_logic;

signal posedgecounter :std_logic_vector((COUNTVALUE - 1)

downto 0);

signal negedgecounter,test :std_logic_vector((COUNTVALUE -

1) downto 0);

begin

-----------------------------

PROCESS(CLK,CLR)

begin

IF ( CLR = '0') THEN

posedgecounter <= (others =>'0');

ELSIF RISING_EDGE(CLK) THEN

posedgecounter <= posedgecounter + 1;

if posedgecounter = conv_std_logic_vector((CLK_DIV_BY -

1),(COUNTVALUE)) then

posedgecounter <= (others =>'0');

end if;

if posedgecounter <= conv_std_logic_vector(((CLK_DIV_BY -

1)/2),(COUNTVALUE)) then

DIV_pos <= '1';

else

DIV_pos <= '0';

end if;

END IF;

END PROCESS;

------------------------------

PROCESS(CLK,CLR)

begin

IF ( CLR = '0') THEN

negedgecounter <= (others =>'0');

ELSIF FALLING_EDGE(CLK) THEN

negedgecounter <= negedgecounter + 1;

if negedgecounter = conv_std_logic_vector((CLK_DIV_BY -

1),(COUNTVALUE)) then

negedgecounter <= (others =>'0');

end if;

if negedgecounter <= conv_std_logic_vector

(((CLK_DIV_BY -1)/2),(COUNTVALUE)) then

DIV_neg <= '1';

else

DIV_neg <= '0';

end if;

END IF;

END PROCESS;

----------------------------------------

DIV<= DIV_pos and DIV_neg;

----------------------------------------

end beh;

**7. Please give a circuit to divide frequency of clock cycle by two?**

a T flip flop act as a frequency divider

Set up time constraint signifies how late the input signal

can arrive before the active edge of the flip-flop. Smaller

the set up time, the better.

Hold time on the other hand signifies how long the value at

the input needs to be held stable after the the active edge.

Again the smaller the hold time, the better.

For estimating maximum clock frequency, set up time is critical.

**9. Explain What is the difference detween ISR & function call?**

in isr there is no return value but in function call there

is return value

**10. Where can we find the sample ASSEMBLY LANGUAGE programs?**

write a c code.

and generate the assembly for it using

cc -S xyz.c -o xyz.S

xyz.Swill contain assembly for your c code with instructions

of the processor of your computer/hardware