Explain What are the five stages in a DLX pipeline?
Submitted by: AdministratorThe instruction sets can be differentiated by
* Operand storage in the CPU
* Number of explicit operands per instruction
* Operand location
* Operations
* Type and size of operands
Submitted by Sowjanya Rao (Sowjanya_Rao@Dell.com)
IF: Instruction Fetch ( from memory) ID: Instruction decode and register read EX: Execution of the operation or address calculation MEM: Data memory access ( i.e accessing the operand) WB: Write Back ( the result)
Submitted by: Administrator
* Operand storage in the CPU
* Number of explicit operands per instruction
* Operand location
* Operations
* Type and size of operands
Submitted by Sowjanya Rao (Sowjanya_Rao@Dell.com)
IF: Instruction Fetch ( from memory) ID: Instruction decode and register read EX: Execution of the operation or address calculation MEM: Data memory access ( i.e accessing the operand) WB: Write Back ( the result)
Submitted by: Administrator
Read Online Computer Architecture Job Interview Questions And Answers
Top Computer Architecture Questions
| ☺ | What is the difference between interrupt service routine and subroutine? |
| ☺ | For a pipeline with n stages, what is the ideal throughput? What prevents us from achieving this ideal throughput? |
| ☺ | Whats the difference between Write-Through and Write-Back Caches? Explain advantages and disadvantages of each? |
| ☺ | What is Cache Coherency? |
| ☺ | What are the components in a Microprocessor? |
Top PC Hardware Categories
| ☺ | Motherboard Interview Questions. |
| ☺ | Basic Computer Interview Questions. |
| ☺ | Embedded Systems Interview Questions. |
| ☺ | A + (Plus) Hardware Interview Questions. |
| ☺ | Computer Architecture Interview Questions. |
