What is the difference between the following two lines of Verilog code?
Submitted by: AdministratorWhat is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.
a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.
Submitted by: Administrator
#5 a = b;
a = #5 b;
#5 a = b; Wait five time units before doing the action for "a = b;".
The value assigned to a will be the value of b 5 time units hence.
a = #5 b; The value of b is calculated and stored in an internal temp register.
After five time units, assign this stored value to a.
Submitted by: Administrator
Read Online Electrical Engineering Job Interview Questions And Answers
Top Electrical Engineering Questions
| ☺ | CO2 fire extinguishers are indicated by the color code |
| ☺ | In a star connected three phase transformer the |
| ☺ | A single-phase double-wound transformer consists of |
| ☺ | A residual current device will disconnect under |
| ☺ | The usual method of insulating core laminations is |
Top Best Engineering Categories
| ☺ | Mechanical Engineering Interview Questions. |
| ☺ | Civil Engineering Interview Questions. |
| ☺ | Chemical Engineering Interview Questions. |
| ☺ | Electrical Engineering Interview Questions. |
| ☺ | Automobile Engineering Interview Questions. |
